1. Field
An embodiment of the present invention relates to the field of integrated circuit fault modeling and more particularly, to a generalized fault model to model random defects and circuit marginalities.
2. Discussion of Related Art
Defects in semiconductor chips are typically modeled as faults with binary behavior for the purposes of generating or grading manufacturing tests. Conventional fault models include the static stuck-at or dynamic transition fault models. These conventional fault models may have several limitations.
For example, certain defective behaviors may manifest only when certain other electrical conditions are satisfied. Because conventional fault models do not provide for a separation of the cause and effect of a test, they may be inadequate to model such defective behaviors.
Additionally, the above-described fault models cannot be used to model defects that manifest at different locations over time depending on the excitation conditions.
For another example, the amount of delay induced in a coupled net may vary depending on the number of aggressor lines involved. The conventional fault models do not provide a straightforward way to refine tests to improve their quality for such a situation.
Further, for some situations, it may be desirable to rank the defective behaviors based on the quality of the test(s) obtained by targeting them. Traditional static stuck-at and dynamic transition fault models do not provide a straightforward way to encode an ordering of a group of defective behaviors such that the detection of one defective behavior is sufficient to detect the fault.
As a final example, dynamic faults are typically activated at a certain phase of the system clock and the fault effect captured by a downstream latch in a future (but not necessarily the next) clock phase. In a design with multiple clock frequencies, the activation-to-capture interval can be different for each clock domain, and at domain interfaces. The conventional dynamic transition fault model(s) does not provide a way to encode the transition delay in terms of number of clock phases to ensure capture at a downstream latch.
With these limitations in mind, it's also important to consider that test generation for the above-described conventional models is a well-researched topic and many tools exist to generate tests on large industrial designs. It is desirable, for any newly proposed fault models, to allow for the development of test generation tools using well-known algorithms.